 The different layers of nMOS are shown in the center here. To the right are the two transistor types and three contacts between layers. On the left are the seven buried contact configurations. |
© Elsevier Science Publishers B.V. (1983). This is the author's version of the work. It is posted here by permission of Elsevier for your personal use. Not for redistribution. The definitive version was published in Proceedings, VLSI '83 (Anceau and Aas, eds.), North Holland, Amsterdam, 1983, pp63-72.
An electrical design aid is described which integrates any number of analysis tools, multiple and mixed technologies, a flexible user interface, and the capability for top-down circuit layout. The system, called Electric, currently has design-rule checking and switch-level simulation, and it handles nMOS, CMOS, Bipolar, and printed circuit board design. Circuits are represented as hierarchical networks of electrically connected and geometrically described components. The wires that connect components have attributes that determine what will happen when the components change. This information is used to ensure that the circuit remains properly connected throughout the hierarchy even when low-level components are modified. Thus, top-down design techniques are encouraged by the hierarchically consistent nature of the database.
Computer-aided electrical design has existed for years and many different systems have been built. Nevertheless, as circuits become more and more complex they swamp the capabilities of less powerful design aids. Frequently changing technologies are creating a need for design aids that are not bound to rigid environments. The growing number of analysis aids must be accommodated in the design environment. Also, the user interface is rarely flexible enough to suit designers. For true flexibility of design, top-down circuit specification must be available so that large pieces of a design can be planned before their contents are specified. Then, as lower-level objects change, the effects are consistently propagated from the bottom-up. The system described here handles multiple technologies, arbitrary analysis aids, has a powerful user interface, and supports top-down design.
One of the problems with today's design aids is their inability to accommodate the ever-increasing number of circuit analysis tools that are in use. Typical design systems consist of many components. After layout, the design is post-processed by a design rule checker, a node extractor, a simulator, a static analyzer, a compacter, a test vector generator, fabrication preparation, and even experimental analysis tools such as circuit and timing verification. In addition to these post-processing steps, there are many pre-processing steps that occur before and during layout. Examples are programmable logic array (PLA) and gate array generators, floor planning systems, cell library searching, wire routing, and many more. To design effectively, the designer needs to understand a complicated set of programs. Each program typically has a different user interface, making the design process difficult to learn. In addition, each program is often un-related to other parts of the system, making user feedback difficult and cryptic.
Another aspect of design systems that is a problem for designers is the user interface and the manner of interaction that it provides. Besides basic human engineering issues, electrical design aids can be categorized along two orthogonal dividing lines that break the systems into four categories. These dividing lines are the text vs. graphics distinction and the connectivity vs. geometry distinction.
Textual design languages are typically used in batch environments where a textually specified circuit is compiled into a layout and plotted for the user's verification. Graphic design languages are more interactive and link the user with a graphics display for immediate visual feedback of the design as it is created. Textual design languages have the advantage that they are often more powerful than graphical languages, especially when that textual language is a superset of a known programming language [5, 26]. Textual languages can be easier to document, parameterize, and transport. In addition, textual design is cheaper because the need for graphic output is reduced and the plotting devices can be shared. Graphic design languages, however, are typically easier to learn and faster to use in producing a circuit. This is because of the immediate feedback provided to the user and because graphics is a closer representation of the designed circuit than is text. Some design systems provide both text and graphics [5, 8, 9, 17, 26].
The other dividing line in electrical design aids is whether the user describes the circuit in a sticks" form of connectivity or a geometric form of placement. Sticks systems require that the circuit be described as a network of dimensionless components connected to each other with wires. The actual size of the components and wires is considered later when the design aid produces a layout. Geometric systems, on the other hand, treat the entire circuit as explicit areas of silicon, metal, etc. There are no components or wires, just the geometry that describes both. Sticks systems have the advantage that electrical connectivity information is available to the design aid for analysis of the circuit. The disadvantage is that the user must rely on the design aid to properly generate an efficient layout of the circuit (or must spend much additional effort describing the exact size and placement of each component). Geometric systems require less intelligence because they are simply managing collections of polygons that describe the circuit without understanding their use.
Current design aids can be viewed in light of the above classifications. Early design aids were textual and geometry based (for example PAL [2], ICLIC [3], and CIF [12]). Many subsequent systems remained geometry based but provided graphics interfaces. Examples are ICARUS [19], Caesar [22], Chipmunk [23], and AGS [1]. Geometry based systems also exist that allow both text and graphics input (Daedalus/DPL [5], SILT [8], and CADDS II [9]).
Printed circuit design systems are typically graphics and connectivity based (for example SUDS [21] and Scald [18]). More recently, the connectivity approach has been used as a basis for textual VLSI layout languages (EARL [15], ALl [16], Sticks & Stones [7], and I [13]). There are even connectivity based systems that allow text and graphics (LAVA/Sedit [17]).
A rare system combines text and graphics design with both connectivity and geometry. Mulga [26] acts like a sticks system but displays and manipulates the fully instantiated geometry. It has a graphics editor and can be used textually with a superset of the C programming language [141.
Todays electrical design aids cover a wide range of interaction styles and design functions. There it little consistency (due to the vast complexity of the field: constantly changing technologies and ever-new approaches to design. An electrical design aid is needed that can grow along all of these lines and provide a uniform design environment.
A new design aid named Electric is described here. It can incorporate all of the analysis aids described above in a uniform manner. Some of these have already been integrated into Electric and others are available simply by programming the correct interface format. To date, there is a design rule checker and two simulators. The user interface, which graphically manipulates the circuit, is treated as an analysis aid. In addition, there is an input/output system that handles textually described circuits and it, too, acts as an analysis aid.
Electric is like Mulga in its use of both connectivity and geometry in the description of a circuit. All electrical components are treated as nodes in a network and they are connected with wires that are the arcs of the network. In addition, the nodes and arcs of this circuit network have geometric information so that proper graphic display is always available during design. Collections of nodes and arcs can be treated as single complex nodes in higher levels of the design hierarchy. A collection of hierarchically connected cells describes a circuit and is contained in a library. Electric provides top-down design by performing bottom-up propagation of changes so that the entire library always remains properly connected. Multiple libraries can be handled for the purpose of updating old designs and collecting cells of a given class.
At the bottom of a circuit hierarchy there are primitive nodes and arcs which are described by the technologies. Technologies, therefore, are the building blocks from which designs are made. They are collections of primitive components with information about how to use them in design. The components vary greatly with the technology: in printed circuit board design the components are logic elements; in MOS the components are single transistors; and in Bipolar the components are the parts of transistors: bases, emitters, and collectors.
Electric allows a hierarchy of cells to be mixed in technology. For example, the VLSI designer can layout a chip in nMOS and then treat an instance of that chip as a node in a printed circuit board design. Simulation and other appropriate analysis aids will cross this technology boundary to provide proper analysis from the computer system level down to the chip transistor level. This is especially useful to VLSI designers who need to consider the pin requirements and proper configuration of their chips.
The remainder of this paper will discuss the three important aspects of Electric: the technologies, the circuit database that provides for top-down design, and the integrated analysis aids. Electric is written in the C programming language and runs on DEC VAX computers. It is expected that the system can be ported to smaller computers for use in a design workstation.
Technologies provide the building blocks of electrical design. In addition to the primitive nodes and arcs, they describe all of the attributes of these components for the analysis aids. Examples of information provided for the nodes and arcs are their functional descriptions, their default sizes, and their connectivity. Frequently the nodes and arcs are described in terms of their common components: geometric layers. Examples of the information provided about layers are design rules and graphical attributes.
Electric currently supports the nMOS, Bulk CMOS, I2L Bipolar, and printed circuit board technologies. To show how technology flexibility provides a useful design environment, the salient aspects of each of these technologies will be discussed.
N-channel Metal Oxide Semiconductor (nMOS) is the technology that has been used most for Electric's applications. This technology has wires that can run in metal, polysilicon, or diffusion. Both enhancement and depletion transistors exist as primitive nodes in the nMOS technology. It is not proper to create a transistor by crossing polysilicon and diffusion wires: a transistor node must be used. This allows Electric to know the functionality of the circuit more precisely. If polysilicon and diffusion wires are crossed, the design rule checker will issue an error. However, since the design rule subsystem is integrally connected to the design process, it can be programmed to insert a transistor node in the proper place.
In addition to the transistors, the nMOS technology provides nodes for connecting layers. There are nodes for connecting metal to diffusion, metal to polysilicon, diffusion to polysilicon (buried contacts) and all three (butting contacts). The three layers on which arcs can run (metal, polysilicon and diffusion) have dummy nodes, called pins, for making arc corners. All layers have pure nodes associated with them so that arbitrary structures can be built. Figure 1 shows the primitive nodes in the nMOS technology These have been shown to be sufficient in the design of moderately large (over 10,000 transistor) chips.
The different layers of nMOS are shown in the center here. To the right are the two transistor types and three contacts between layers. On the left are the seven buried contact configurations. |
Complementary Metal Oxide Semiconductor (CMOS) is much like nMOS except that instead of enhancement and depletion mode transistors, there are N-channel and P-channel transistors. These transistors are located in P-well and P+ implant regions on the chip. Metal and polysilicon can run in and out of these areas, but the diffusion layer is sensitive to implant presence. In order to relieve the designer of correct implant placement, this technology provides two types of diffusion wires: N+ diffusion in P-well and P+ diffusion in N substrate. Also provided are two types of metal-to-diffusion contacts and two types of diffusion pins for these cases.
The existence of nodes and arcs that include their surrounding implant means that these implants never have to be explicitly described to the design aid. In connecting a N-channel transistor (in P-well) to a metal-diffusion contact in P-well, the connecting arc and both nodes will include the proper amount of P-well surround. Figure 2 shows the primitive nodes for the CMOS technology, including metal-diffusion split contacts that cross implant boundaries to connect with the substrate and P-well.
 The different layers of CMOS are shown down the center here. To the left are the two transistor types and the split contacts for substrate connection. On the right are the layer contacts: four metal-to-diffusion contacts for the two implant combinations and a metal-to-polysilicon contact in the center right. |
Integrated Injecter Logic (I2L) is one of the bipolar technologies in use today. Unlike the MOS technologies, bipolar transistors may have multiple collectors, gates, and emitters of varying shape and may share these components among multiple transistors. Thus, it is not feasible to provide a limited number of transistors as primitive nodes in the technology. Rather, the transistor must be reduced to its components to provide flexible design. The primitive transistor node is therefore an empty region of buried implant. Attached to that can be collector, base, and emitter nodes of arbitrary shape and size.
This particular technology provides two layers of metal and a "via" node for connecting them. In addition to carte-blanch transistors, there are resistors of a similar nature. Figure 3 summarizes the components of this technology.
 The different layers of I2L are shown on the left here. On the right are the three components of transistors: emitters, bases, and collectors; and a via for connecting the different metal layers. Transistors are constructed by placing the components on the buried layer. |
The printed circuit technology can do logic design or actual printed circuit layout. For logic design, the technology provides logic components (NAND, NOR, NOT, etc.) and wires as primitive components. For printed circuit layout, a library of over 700 chips is available which describes many of the most common chips in use today. Information on the multiple layers of a printed circuit board can also be specified. Cells from other technologies can be incorporated as packages and used here. Because the basic unit of layout is measured in true distance (centimicrons), technology mixing gives proper size information. So, when a VLSI circuit is placed inside a TTL package, the true size of that circuit relative to the package bounds is displayed. Very little use has been made of this technology because there are no available wire list generators, placement and routing aids, or other support tools.
At the heart of Electric is a model of circuit representation and modification. This model treats a circuit as a hierarchical network of electrical components, connected with wires. A set of operations can be performed on the components resulting in electrically consistent changes in the network. The centralization of circuit management simplifies the addition of new technologies and analysis aids.
Each technology provides the database with a set of primitive circuit components, called nodes. The primitive nodes have ports for arc connections in fixed locations, relative to the size of the node. For example, the MOS transistor node has four ports at the source, drain, and two gates. If the transistor is scaled to have a larger channel length, the source and drain ports move farther apart and the gate ports elongate to allow connection anywhere along the aide. Also provided by the technology is a set of wire types, called arcs. Each arc connects exactly two different ports and each port is typed to indicate the class of arcs to which it may connect. To bend an arc or run it between more than two points, multiple arcs and intermediate pin nodes must be used. An arc cannot exist without making a connection. Therefore if a node is removed from the database, all arcs connected to it are also removed.
Hierarchy of circuit design is achieved by packaging a group of nodes and arcs into a cell which acts as a complex node. Like primitive nodes, cells have ports for arc connections. These are simply exported ports from nodes inside the cell. Ports on complex nodes retain all of the characteristics of the ports on the primitive nodes from which they came, even when the ports are further exported up the hierarchy. As the internal nodes change and their exported ports move, the cell, its ports, and the arcs connected to it change. If an internal port is unported , then all arcs connected to instances of the cell at the exported port are deleted.
Modification of the circuit network is restricted to transformation of nodes. Nodes can be moved, rotated, mirrored, or scaled. When the ports of a node move due to a transformation, the arcs attached at those ports are also modified. Depending on the attributes of the arcs, the nodes at the other end may also be transformed. The circuit database manager converts every node transformation into a series of database changes that consistently updates the circuit.
There are two arc attributes that affect circuit modification: orthogonality and rigidity. An orthogonal arc (sometimes called a Manhattan arc) is one that must remain horizontal or vertical through all changes. If two nodes are connected with an orthogonal arc that is vertical and the bottom node moves to the left, then the top node (and the connecting arc) will also move left. If the arc were non-orthogonal, then the top node would remain where it is and the arc would rotate to make the connection (see Figure 4).
 On the left, three nMOS nodes are connected with two arcs. The transistor at the bottom is connected with a polysilicon arc to a metal-polysilicon contact which is then connected with a metal arc to a metal-diffusion contact. The polysilicon arc is orthogonal but the metal arc is not. The right side shows the result of translating the transistor node to the left. The same effect could be achieved by translating the metal-polysilicon contact. |
The other arc attribute that affects circuit modification is rigidity. A rigid arc cannot stretch and connects its two nodes in a fixed configuration. If two nodes are connected with a rigid arc and one moves to the lower-right, then the other node and the arc will move the same amount. If one of the nodes rotates, the other node will spin about the center of the modified node, causing this other node to rotate and translate (see Figure 5).
 On the left, four nMOS nodes are connected with three arcs. The butting contact at the bottom is connected with a metal arc to a metal pin which is connected with another metal arc to a metal-polysilicon contact. The contact is then connected with a polysilicon arc to a transistor. Both metal arcs are rigid, but the polysilicon arc is not. The right side shows the result of mirroring the butting contact about the horizontal axis. Both the metal pin and the metal-polysilicon contact also get mirrored, but they are symmetric and therefore show no effects. |
There are other arc attributes that are useful in design. The notion of temporary rigidity is available for overriding specified constraints in order to effect once-only change. For example, when compacting (or spreading apart) a circuit, the arcs that cross the line of compaction are made temporarily non-rigid and all other arcs are made temporarily rigid. Then, moving a single node will compact properly and leave the arc attributes as they were.
Although not implemented now, it would be useful to have minimum and maximum length attributes that allow arcs to be non-rigid within these limits. Also eight-way orthogonality, in which 45° arcs were allowed, would be useful.
Most arcs begin as non-rigid and orthogonal so that Manhattan designs can easily be made. However this and other default attributes are set by the technology and changeable by the user.
Because of the hierarchy, a single database modification can manifest itself as a large number of changes. If a node transforms, the cell in which it resides may change size which will cause all instantiations of this cell to scale. If the moved node has an exported port (or is connected to a node with an exported port in such a way that the port moves) then the ports on instances of the cell will also change. If, for example, instances of the changed cell are connected to each other with rigid arcs, then their positions will change because the rigid arcs hold them a constant distance apart. This translation will cause the cell with the instances to scale, and the entire network will recursively alter. Figure 6 shows an example of such a hierarchical change. In overconstrained cases, an arc may have to be jogged to retain electrical connectivity. The database will insert new pin nodes and arcs to make this jog.
 The top half of this figure shows three levels of hierarchical design. At the left is a "gate" cell; next to that is a cell with three instances of the gate tied together; and to the right of that is two instances of the previous cell tied together (one is mirrored horizontally). The top right shows all three levels of the hierarchy fully instantiated. The bottom half shows the same views of these hierarchical levels after a single change has been made: the transistor in the gate cell has been sealed from 2x2 to 2x6 in size. Because of the attributes of the connecting arcs, the entire hierarchy expands to accommodate this change. |
Every change to the database comes from one of the analysis aids. The change, and all associated side-effects, are packaged into a change-batch that is preserved by the database. When the analysis aid finishes issuing changes, the collected modifications are broadcast to all of the analysis aids. It is possible to request that the database retract a batch of changes. A variable sized list of batches is retained and can be used to undo any modifications. Because of this facility, users are less timid about trying circuit modifications when they know that whatever is done can be undone.
Electric provides a useful environment for writing analysis aids. Since both connectivity and geometric information are available from the database, all commonly used forms of circuit description are present. Node extraction and rasterization pre-processors are unnecessary as are input and output facilities. The analysis aid writer need only program the "inner loop" which is a fraction of the amount of code typically needed.
Although not currently implemented, background processing is an important consideration for analysis aids. As the number of these systems increases, their activity will overload Electric, causing slow response. An analysis aid should be able to run asynchronously with the design activity. In a completely distributed system, each analysis aid could have its own processor. In single-processor applications, it is sufficient to have only two partitions: the foreground design activity and, in the background, all of the long-running analysis aids. Regardless of the implementation, distributed database updates becomes a non-trivial problem beyond the scope of this paper.
The rest of this section outlines the existing analysis aids and their capabilities. At the end is a list of possible analysis aids that do not presently exist in Electric.
The user interface is a highly flexible and powerful control mechanism. It can support a color display with a pointing device (tablet, mouse, etc.) and a command terminal. However, it does not need all of these devices to function and can tolerate the absence of any component.
Commands to the user interface can be issued via tablet buttons, menu entries, single keyboard letters, or full keyboard commands. All commands are really full keyboard commands, but can be dynamically bound to buttons, menu entries, or keystrokes. Thus, the interface can be tailored to operate in any manner and can mimic other design aids.
The command terminal supports many useful features. To help with command input, Electric requires only as many characters as are unique to a keyword and fills in the rest. The system will also provide a list of keywords that match what has been typed. An on-line help facility explains all commands individually and by category. Parameterized macros and command files are available.
The graphics display also has much of interest. It draws on a scalable lambda grid [19] and permits multiple windows onto the design. The menu entries can be located anywhere on the display and can be scaled to fit any number of commands. Arbitrary symbols can be placed in the entries to help identify their associated commands.
Perhaps the most interesting aspect of the user interface is its portability. The color display and tablet control is done through a device-independent subroutine package modeled after the SIGGRAPH Core System [24]. This package currently supports ten different graphics devices and is adaptable to a wide variety of displays.
The design rule checker is an incremental analysis aid that watches all changes and responds immediately to errors. It currently works at only one level of hierarchy at a time and thus is useful only for leaf-cell design. Whenever an object is created or modified, the layers that comprise it are compared with layers of other objects in the vicinity. Rasterization is not done: instead of examining the object point-by-point, bounding box comparisons are made. This is less efficient when checking a large design, but more efficient when done incrementally.
The design rule checker also keeps track of electrical connectivity so that it will not complain about the proximity of objects that are really allowed to overlap. Errors are displayed on the command terminal, but currently no correction is done.
Simulation is an example of an analysis tool that docs not have to be written. Instead, two existing simulators, MARS, a hierarchical switch-level simulator [25] and ESIM, an event-based switch-level simulator [4] have been interfaced. When simulation is desired, the analysis aid writes the circuit description suitable for the simulator and helps the user to communicate with the program. Thus, an analysis tool can be integrated without major re-writing.
The input/output system is viewed as an analysis aid because of the wide variety of description formats that it can potentially handle. Textual languages can be more powerful than graphical ones, so a separate analysis aid is needed to handle them. The current system can read and write binary forms of the circuit for maximum efficiency. It can also read and write textual forms of the circuit that are more portable.
The input/output system can currently write CIF files [12] but cannot read them. CIF input requires node extraction which makes it much more difficult than CIF output.
In addition to filling in the missing pieces of the existing analysis aids, it would be useful to have the following facilities:
Electric is a flexible design aid that can accommodate a diverse range of needs. In its current state, it has enough functionality for the design of VLSI chips and has been so used. Electric also provides a workbench for testing new circuit analysis algorithms. Most important is its model of circuit representation and change that allows top-down design and ease of circuit modification. Combined with a powerful user interface and a variety of technologies, Electric is a valuable system for circuit design.